Detecting reducible registers

Details Detecting reducible registers Detecting reducible registers

2006-02-22

2008-08-12

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07412677

ABSTRACT:
Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition. The tests determine if the logic condition holds. If the logic condition of a set is found to be violated, the registers may be moved to another set having a different logic condition or removed completely. The registers remaining are potentially reducible. The reducibility of the registers is verified via Boolean analysis by verifying the logic conditions of a register set for each register. If a register does not pass verification, it then may be moved to a different set having a different logic condition or removed completely. The sets that pass verification are reducible.

REFERENCES:
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patent: 6336205 (2002-01-01), Kurokawa et al.
Higuchi, Hiroyuki et al.; “An Implication-based Method to Detect Multi-Cycle Paths in Large Sequential Circuits”; 6 pages, DAC, Jun. 2002.
Krohm, Florian et al.; “The Use of Random Simulation in Formal Verification”; 1996, IEEE, pp. 371-376.
Zhang, Jin S. et al.; “Simulation and Satisfiability in Logic Synthesis”; 8 pages, (NSF, 2005).

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