Methods and apparatus for serially connected devices

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

Reexamination Certificate

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C326S046000

Reexamination Certificate

active

07436217

ABSTRACT:
Apparatus and methods for processing a clock input signal with a clock regeneration circuit to provide a clock output signal for coupling to a cascaded device. The clock output signal has a period substantially equal to the period of the clock input signal and a duty cycle independent of the duty cycle of the clock input signal. In one embodiment, the clock regeneration circuit includes a one-shot and a buffer. Also described are apparatus and methods for aligning a data output signal of a cascaded device to non-clock-triggering edges of a selected one of the clock input signal and the clock output signal.

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