Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-05-05
2008-08-26
Landau, Matthew C (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S316000, C257SE29300
Reexamination Certificate
active
07417278
ABSTRACT:
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.
REFERENCES:
patent: 4814840 (1989-03-01), Kameda
patent: 5045490 (1991-09-01), Esquivel et al.
patent: 5162247 (1992-11-01), Hazani
patent: 5173436 (1992-12-01), Gill et al.
patent: 5414287 (1995-05-01), Hong
patent: 5422292 (1995-06-01), Hong et al.
patent: 5453637 (1995-09-01), Fong-Chun et al.
patent: 5495441 (1996-02-01), Hong
patent: 5643814 (1997-07-01), Chung
patent: 5801083 (1998-09-01), Yu et al.
patent: 6008078 (1999-12-01), Zhang
patent: 6071777 (2000-06-01), Chen
patent: 6159801 (2000-12-01), Hsieh et al.
“Silicon Processing forhtr VLSI Era, vol. 2: Process Integration” Wolf et al., Lattice Press 1990. pp. 327-332.
Hsieh Chia-Ta
Kuo Di-Son
Lin Yai-Fen
Sung Hung-Cheng
Yeh Jack
Landau Matthew C
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
LandOfFree
Method to increase coupling ratio of source to floating gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to increase coupling ratio of source to floating gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to increase coupling ratio of source to floating gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4001744