DRAM including segment read circuit

Details DRAM including segment read circuit DRAM including segment read circuit

2007-10-23

2008-10-28

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S189050, C365S189150, C365S189170, C365S194000, C365S207000, C365S230030

Reexamination Certificate

active

07443714

ABSTRACT:
A time-domain sensing scheme is introduced for reading a DRAM cell and bit lines are multi-divided for reducing parasitic loading. Thereby lightly loaded bit line is quickly charged by a selected memory cell when reading data “1”. The charged voltage is amplified by a segment read circuit, which quickly changes an output of a block read circuit. In contrast, the bit line is discharged when reading data “0”, so that impedance of the segment read circuit is increased, which slowly changes the output of a block read circuit. Hence, data “1” is arrived early but data “0” is not arrived to a latch circuit, because the latch is locked by a locking signal based on data “1”. Furthermore storage capacitor is reduced to drive short bit line only. Additionally, various alternatives are described.

REFERENCES:
patent: 5357474 (1994-10-01), Matano et al.
patent: 5822260 (1998-10-01), Tamaki
patent: 6456521 (2002-09-01), Hsu et al.
patent: 6512717 (2003-01-01), Eto et al.
patent: 6930940 (2005-08-01), Haraguchi
patent: 7292496 (2007-11-01), Akiba et al.

Affiliated with

Also associated with

Rating

DRAM including segment read circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM including segment read circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM including segment read circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3994700