Versatile register file design for a multi-threaded...

Details Versatile register file design for a multi-threaded... Versatile register file design for a multi-threaded...

2004-05-13

2008-08-26

Dollinger, Tonia L. M. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Context preserving (e.g., context swapping, checkpointing,...

C712S229000

Reexamination Certificate

active

07418582

ABSTRACT:
A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.

REFERENCES:
patent: 4425616 (1984-01-01), Woodell
patent: 5446854 (1995-08-01), Khalidi et al.
patent: 5465337 (1995-11-01), Kong
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5596293 (1997-01-01), Rogers et al.
patent: 5717885 (1998-02-01), Kumar et al.
patent: 5761511 (1998-06-01), Gibbons et al.
patent: 5802341 (1998-09-01), Kline et al.
patent: 5842225 (1998-11-01), Kohn
patent: 5860147 (1999-01-01), Gochman et al.
patent: 5895487 (1999-04-01), Boyd et al.
patent: 5899994 (1999-05-01), Mohamed et al.
patent: 5900011 (1999-05-01), Saulsbury et al.
patent: 5911071 (1999-06-01), Jordan
patent: 5918005 (1999-06-01), Moreno et al.
patent: 5933627 (1999-08-01), Parady
patent: 5941977 (1999-08-01), Panwar et al.
patent: 5953010 (1999-09-01), Kampe et al.
patent: 5956756 (1999-09-01), Khalidi et al.
patent: 5991790 (1999-11-01), Shah et al.
patent: 6016542 (2000-01-01), Gottlieb et al.
patent: 6044446 (2000-03-01), Joy et al.
patent: 6081880 (2000-06-01), Sollars
patent: 6092154 (2000-07-01), Curtis et al.
patent: 6092175 (2000-07-01), Levy et al.
patent: 6098169 (2000-08-01), Ranganathan
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6141692 (2000-10-01), Loewenstein et al.
patent: 6185660 (2001-02-01), Mulla et al.
patent: 6199142 (2001-03-01), Saulsbury et al.
patent: 6219723 (2001-04-01), Hetherington et al.
patent: 6308279 (2001-10-01), Toll et al.
patent: 6311261 (2001-10-01), Chamdani et al.
patent: 6314563 (2001-11-01), Agesen et al.
patent: 6374349 (2002-04-01), McFarling
patent: 6408368 (2002-06-01), Parady
patent: 6449694 (2002-09-01), Burgess, Jr. et al.
patent: 6493819 (2002-12-01), Mahurin et al.
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 6578137 (2003-06-01), Parady
patent: 6609193 (2003-08-01), Douglas et al.
patent: 6671707 (2003-12-01), Hudson et al.
patent: 6700410 (2004-03-01), Ebergen
patent: 6700825 (2004-03-01), Ebergen
patent: 6715057 (2004-03-01), Kessler et al.
patent: 6718438 (2004-04-01), Lewis et al.
patent: 6718494 (2004-04-01), Jamil et al.
patent: 6732143 (2004-05-01), Saulsbury
patent: 6751655 (2004-06-01), Deutsch et al.
patent: 6766428 (2004-07-01), Saulsbury et al.
patent: 6772369 (2004-08-01), Smith et al.
patent: 6779087 (2004-08-01), Saulsbury et al.
patent: 6802039 (2004-10-01), Quach et al.
patent: 6816961 (2004-11-01), Rice et al.
patent: 6823473 (2004-11-01), Mukherjee
patent: 6854075 (2005-02-01), Mukherjee et al.
patent: 2001/0047468 (2001-11-01), Parady
patent: 2002/0052926 (2002-05-01), Bush et al.
patent: 2002/0056037 (2002-05-01), Wolrich et al.
patent: 2002/0087840 (2002-07-01), Kottapalli et al.
patent: 2002/0129309 (2002-09-01), Floyd et al.
patent: 2002/0162092 (2002-10-01), Ravichandran
patent: 2003/0002974 (2003-01-01), Gunnarsson
patent: 2003/0097518 (2003-05-01), Kohn et al.
patent: 2003/0131277 (2003-07-01), Taylor et al.
patent: 2004/0003211 (2004-01-01), Damron
patent: 2004/0006633 (2004-01-01), Chandra et al.
patent: 2004/0034853 (2004-02-01), Gibbons et al.
patent: 2004/0073778 (2004-04-01), Adiletta et al.
patent: 2004/0088487 (2004-05-01), Barroso et al.
patent: 2004/0098496 (2004-05-01), Wolrich et al.
patent: 2004/0148472 (2004-07-01), Barroso et al.
patent: 2005/0114856 (2005-05-01), Eickemeyer et al.
patent: 2005/0193283 (2005-09-01), Reinhardt et al.
The SPARC Architecture Manual, 1992, SPARC international, Inc., Version 8, pp. 1-41.
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi, “Reducing the Complexity of the Register File in Dynamic Superscalar Processors,” International Symposium on Microarchitecture, Proceedings of the 34thAnnual ACM/IEEE International Symposium on Microarchitecture, pp. 23-248, Mar. 2001.
Peter Magnusson, “Understanding Stacks and Registers in the SPARC Archiecture(s),” http://www.sics.se/˜psm/sparkstack.html, Apr. 1997.
Mukherjee, S. et al., “Detailed Design and Evaluation of Redundant Multithreading Alternatives,” Computer Architecture, 2002, Proceedings 29th Annual International Symposium, pp. 1-12.
Reinhardt, S.K. et al., “Transient Fault Detection via Simultaneous Multithreading,” Computer Architecture, 2000, Proceedings of the 27th International Symposium, 12 pages.
Kharbutli, M. et al., “Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses,” 10th Annual Symposium on High Performance Computer Architecture, Feb. 14-18, 2004, 12 pages.
Kalla, R. et al., “IBM Power5 Chip: A Dual-Core Multithreaded Processor,” Published by the IEEE Computer Society, Mar.-Apr. 2004, pp. 40-47.
Watanabe, K. et al., “Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading,” IEEE, 2001, pp. 122-129.
Hennessy, J. et al., “Computer Architecture: A Quantitative Approach,” Morgan Kaufmann, third edition, 2002, pp. A-68 to A-77.
Hoe, J.C. “Superscalar Out-of-Order Demystified in Four Instructions,” 2003, http://www.ece.cmu.edu/˜jhoe/distribution/2003/wcae03.pdf, pp. 1-6.
Chen, S. et al., “Out-of-Order Memory Accesses Using a Load Wait Buffer,” http://www.ece.cmu.edu/˜schen1/18-741—final—report.pdf, pp. 1-8.

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