Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-16
2008-10-28
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S016000, C703S019000
Reexamination Certificate
active
07444607
ABSTRACT:
A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching the tolerance for when a timing error occurs for a cell in each layout block with a worst condition of one of the corresponding cells in the layout blocks, and inserting a timing adjustment cell within a range of the matched tolerance of each cell to adjust the timing error. This method ensures the correction of hold errors and setup errors in an integrated circuit designed with a hierarchical design technique.
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Ando Hiroaki
Yoshimura Terumi
Fujitsu Limited
Kik Phallaka
Staas & Halsey , LLP
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