Power transistor including a leadframe and a semiconductor...

Details Power transistor including a leadframe and a semiconductor... Power transistor including a leadframe and a semiconductor...

2005-08-30

2008-09-23

Lewis, Monica (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000

Reexamination Certificate

active

07427792

ABSTRACT:
A power transistor includes a leadframe and a semiconductor chip arranged on the leadframe. The top side of the semiconductor chip has a drain contact-making layer, and the underside of the semiconductor chip has a source contact-making layer. The source contact-making layer bears directly on the leadframe. A gate contact-making layer is provided on the top side of the semiconductor chip. The gate contact-making layer is electrically connected via at least one trench filled with conductive material to gate zones provided in the lower region of the semiconductor chip.

REFERENCES:
patent: 5293056 (1994-03-01), Terashima
patent: 6072215 (2000-06-01), Kawaji et al.
patent: 6114768 (2000-09-01), Gaul et al.
patent: 6242787 (2001-06-01), Nakayama et al.
patent: 6414389 (2002-07-01), Hume et al.
patent: 6444528 (2002-09-01), Murphy
patent: 2006/0017100 (2006-01-01), Bol et al.
patent: WO 99/43027 (1999-08-01), None
Peter Van Zant, Microchip Fabrication, 2000, Fourth Edition, p. 511.

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