Semiconductor memory device having advanced test mode

Details Semiconductor memory device having advanced test mode Semiconductor memory device having advanced test mode

2007-12-26

2008-10-21

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07441156

ABSTRACT:
An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and testing a write operation of the semiconductor memory device.

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