Delay locked operation in semiconductor memory device

Details Delay locked operation in semiconductor memory device Delay locked operation in semiconductor memory device

2006-09-20

2008-09-30

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S230080, C365S222000

Reexamination Certificate

active

07430143

ABSTRACT:
A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling a delay of the internal clock such that a data output timing is synchronized with the system clock; a data output buffer for synchronizing data with the delay locked internal clock, thereby outputting the data, and a clock buffer control unit, responsive to a previous operation state, for generating an enable signal controlling the on/off switching of the clock buffer.

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Korean Office Action, issued in Korean Patent Application No. 10-2006-0049114, dated on Feb. 4, 2008.

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