Data packing in a 32-bit DMA architecture

Details Data packing in a 32-bit DMA architecture Data packing in a 32-bit DMA architecture

2006-07-07

2008-10-28

Shin, Christopher B (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S033000, C710S065000, C710S308000

Reexamination Certificate

active

07444442

ABSTRACT:
A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packing criteria and analysing the data pattern and determining the impact of offset direction on data packing. If the packing criteria are met, the data is compacted and fetched in four bytes or two half-words in one transaction by performing a full-word transfer instead of a partial transfer. If the packing criteria are not met, a single byte or a single half word is fetched. This invention provides a system for reducing data transfer overheads. The system comprises of an external address generation unit for generating external memory addresses and corresponding byte enables and a read local address generation unit for generating internal memory addresses and corresponding byte enables.

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