Shared memory synchronization systems and methods

Details Shared memory synchronization systems and methods Shared memory synchronization systems and methods

2006-06-12

2008-09-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S063000, C365S233100

Reexamination Certificate

active

07430139

ABSTRACT:
The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.

REFERENCES:
patent: 7016213 (2006-03-01), Reeves et al.
patent: 7020757 (2006-03-01), Ruhovets et al.

Affiliated with

Also associated with

Rating

Shared memory synchronization systems and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shared memory synchronization systems and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared memory synchronization systems and methods will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3990975