FinFET device with multiple channels

Details FinFET device with multiple channels FinFET device with multiple channels

2004-01-13

2008-10-07

Dang, Trung (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000, C257S401000, C257SE29130

Reexamination Certificate

active

07432557

ABSTRACT:
A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

REFERENCES:
patent: 4996574 (1991-02-01), Shirasaki
patent: 5115289 (1992-05-01), Hisamoto et al.
patent: 5338959 (1994-08-01), Kim et al.
patent: 5545586 (1996-08-01), Koh
patent: 5705414 (1998-01-01), Lustig
patent: 5932911 (1999-08-01), Yue et al.
patent: 6063688 (2000-05-01), Doyle et al.
patent: 6177299 (2001-01-01), Hsu et al.
patent: 6180441 (2001-01-01), Yue et al.
patent: 6232622 (2001-05-01), Hamada
patent: 6358827 (2002-03-01), Chen et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6514819 (2003-02-01), Choi
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6537880 (2003-03-01), Tseng
patent: 6562665 (2003-05-01), Yu
patent: 6583469 (2003-06-01), Fried et al.
patent: 6645797 (2003-11-01), Buynoski et al.
patent: 6657259 (2003-12-01), Fried et al.
patent: 6689650 (2004-02-01), Gambino et al.
patent: 6696713 (2004-02-01), Ishibashi
patent: 6716686 (2004-04-01), Buynoski et al.
patent: 6770516 (2004-08-01), Wu et al.
patent: 6794718 (2004-09-01), Nowak et al.
patent: 2001/0005022 (2001-06-01), Ogura
patent: 2002/0011612 (2002-01-01), Hieda
patent: 2002/0043690 (2002-04-01), Doyle et al.
patent: 2002/0060338 (2002-05-01), Zhang
patent: 2002/0153587 (2002-10-01), Adkisson et al.
patent: 2003/0042542 (2003-03-01), Maegawa et al.
patent: 2003/0178677 (2003-09-01), Clark et al.
patent: 2004/0036126 (2004-02-01), Chau et al.
patent: 2004/0099885 (2004-05-01), Yeo et al.
patent: 2005/0020020 (2005-01-01), Collaert et al.
patent: 2005/0073060 (2005-04-01), Datta et al.
patent: 1 202 335 (2002-05-01), None
patent: 1 383 164 (2004-01-01), None
patent: 4-192564 (1992-07-01), None
patent: 04192564 (1992-07-01), None
U.S. Appl. No. 10/726,569; filed Dec. 4, 2003; entitled: “Systems and Methods for Forming Multiple Fin Structures Using Metal-Induced-Crystallization”; 23 pages.
U.S. Appl. No. 10/405,343; filed Apr. 3, 2003; entitled: “Method for Forming Structures in Finfet Devices”; 31 pages.
U.S. Appl. No. 10/754,515 and Preliminary Amendment; filed Jan. 12, 2004; entitled: “Finfet Device With Multiple Fin Structures”; 20 pages.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.

Affiliated with

Also associated with

Rating

FinFET device with multiple channels does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FinFET device with multiple channels, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FinFET device with multiple channels will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3989381