Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-07-27
2008-05-13
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711S151000, C711S216000, C711S163000, C709S203000
Reexamination Certificate
active
07373459
ABSTRACT:
A congestion control and avoidance method including a method check step of determining whether the request contents is cacheable or uncacheable on the basis of the request inputted from the client terminal, a first Uniform Resource Identifier (URI) check step of, when it is determined that the request contents is cacheable in the method check step, checking a URI included in the request from the client terminal to determine whether the request contents is cacheable or uncacheable, a first URI hash search step of, when it is determined that the request contents is cacheable based on determination of the first URI check step, searching a URI hash to determine to execute any of regular caching, priority caching and access limitationing operation, and a step of executing any of the regular caching, priority caching and access limitationing operation according to determination in the first URI hash search step.
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Aoki Hideo
Nishikado Takashi
Noda Fumio
Takahashi Yasuhiro
Takeshima Yoshiteru
Hitachi , Ltd.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
Peikari B. James
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