Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-12-30
2008-09-30
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000
Reexamination Certificate
active
07430695
ABSTRACT:
A register file device has a memory array, a scan connection configuration circuit, a file writing unit, a file reading unit, and a scan control circuit. The memory includes first storage devices which are obtained by adding shift transfer gate and an output gate to a master flip-flop only latch in a conventional register file using master flip-flop only latch storage devices, and a scan connection configuration circuit and a scan control circuit using master flip-flop only second storage devices are added thereto to realize the scan function of internally constituting a shift register and reading contents thereof in testing. The size of the register file is reduced by using master flip-flop only latch storage devices, and a high test/diagnosis efficiency is achieved by using the internal scan function in master-slave type flip-flop (2 latches) storage devices.
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“A Current-Sensed High-Speed and Low-Power First-In-First-Out Memory Using a Wordline/Bitline-Swapped DualPport SRAM Cell” by Shibata et al. IEEE Journal of Solid-State Circuits, Pub Date: Jun. 2002 vol. 37, Issue: 6 On pp. 735-750 ISSN: 0018-9200 INSPEC Accession No. 7297338.
Britt Cynthia
Staas & Halsey , LLP
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