Reducing storage data transfer interference with processor...

Details Reducing storage data transfer interference with processor... Reducing storage data transfer interference with processor...

2005-06-23

2008-05-13

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S323000

Reexamination Certificate

active

07373534

ABSTRACT:
Systems and methods of managing power consumption provide for placing a processor in a non-snoopable state while a storage interface associated with the processor is enabled for bus mastering. In one embodiment, the bus mastering results in traffic between the storage interface and a storage device, where the traffic is monitored and the processor is placed a snoopable state when traffic is moving, and in the non-snoopable idle state if the traffic ceases for a period of time.

REFERENCES:
patent: 2006/0200690 (2006-09-01), Cline et al.

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