Methods of computer power status management and computers...

Details Methods of computer power status management and computers... Methods of computer power status management and computers...

2005-07-14

2008-05-20

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S320000

Reexamination Certificate

active

07376850

ABSTRACT:
A method of computer power state management. When an operating system thereof is idle and the processor thereof transits to a clock-suspended power state (C3/C4 state), an arbitrary bit is asserted to prevent requests from being passed through the Northbridge. When the processor is in the C3/C4 state, if a break event is received, the Southbridge transmits the break event to the Northbridge and changes the processor state from C3/C4 to C0 simultaneously. The break event is subsequently transmitted to the processor when the arbitrary bit is disabled.

REFERENCES:
patent: 6243817 (2001-06-01), Melo et al.
patent: 7225346 (2007-05-01), Kawano et al.
patent: 2006/0047986 (2006-03-01), Kurts et al.

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