System and method for contention-based cache performance...

Details System and method for contention-based cache performance... System and method for contention-based cache performance...

2005-10-27

2008-05-27

Bragdon, Reginald G. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S122000

Reexamination Certificate

active

07380068

ABSTRACT:
A data processing unit, method, and computer-usable medium for contention-based cache performance optimization. Two or more processing cores are coupled by an interconnect. Coupled to the interconnect is a memory hierarchy that includes a collection of caches. Resource utilization over a time interval is detected over the interconnect. Responsive to detecting a threshold of resource utilization of the interconnect, a functional mode of a cache from the collection of caches is selectively enabled.

REFERENCES:
patent: 6701416 (2004-03-01), Arimilli et al.
patent: 2002/0169931 (2002-11-01), Krick et al.

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