Method and program for generating layout data of a...

Details Method and program for generating layout data of a... Method and program for generating layout data of a...

2006-02-03

2008-05-06

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07370314

ABSTRACT:
A method for generating layout data of a semiconductor integrated circuit includes applying optical proximity correction conditions to cells so as to generate cell patterns, selecting cell patterns to correspond cells, based on layout information of cells along a specified signal propagating path; calculating delay times for the signal propagating path for combinations of cell patterns; selecting a combination of cell patterns, based on lengths of the calculated delay times and the allowable delay time; and generating layout data of the signal propagating path using the selected combination.

REFERENCES:
patent: 6459487 (2002-10-01), Chen et al.
patent: 2005/0250022 (2005-11-01), Kotani
patent: 2005/0273754 (2005-12-01), Nojima

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