Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-22
2008-05-27
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07380221
ABSTRACT:
A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.
REFERENCES:
patent: 6148436 (2000-11-01), Wohl
R. Rudell et al., “Espresso-MV Algorithms for Multiple-Valued Logic Minimization”, article, 1985, pp. 230-233, Dept. of Electrical Engineering & Computer Sciences, University of California, Berkeley, CA, USA.
Baumgartner Jason Raymond
Kanzelman Robert Lowell
Mony Hari
Paruthi Viresh
Dillon & Yudell LLP
Do Thuan
Salys Casimer K.
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