Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2005-12-22
2008-05-06
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S230030, C365S230060
Reexamination Certificate
active
07369445
ABSTRACT:
A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.
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Notice to Submit a Response for Korean Patent Application No. 2003-0008327 mailed on Mar. 27, 2006.
Kyung Kye-hyun
Lee Kee-hoon
Yoo Chang-sik
Myers Bigel Sibley & Sajovec P.A.
Nguyen Tuan T.
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