Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-02-11
2008-03-04
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S142000, C711S143000, C710S107000, C710S109000, C710S112000
Reexamination Certificate
active
07340568
ABSTRACT:
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
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Goodman Benjiman L.
Guthrie Guy L.
Starke William J.
Stuecheli Jeffrey A.
Williams Derek E.
International Business Machines - Corporation
Roberts-Gerhardt Diana
Savla Arpan
Shah Sanjiv
Voigt, Jr. Robert A.
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