Semiconductor device, driver circuit and manufacturing...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S350000, C257S378000, C257S409000, C257SE29255, C257SE29174, C257SE29197, C257SE21415, C438S197000, C438S202000, C438S479000

Reexamination Certificate

active

07339236

ABSTRACT:
The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n−type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

REFERENCES:
patent: 5359221 (1994-10-01), Miyamoto et al.
patent: 5656844 (1997-08-01), Klein et al.
patent: 5994739 (1999-11-01), Nakagawa et al.
patent: 6872642 (2005-03-01), Oda et al.
patent: 2006/0118902 (2006-06-01), Ikuta et al.
patent: 2006/0220130 (2006-10-01), Sato et al.
patent: 2007/0090451 (2007-04-01), Lee
patent: 11-87728 (1999-03-01), None
patent: 2003-197919 (2003-07-01), None

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