Set of masks, method of generating mask data and method for...

Details Set of masks, method of generating mask data and method for... Set of masks, method of generating mask data and method for...

2004-03-25

2008-03-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07350181

ABSTRACT:
A method of generating mask data, for a set of masks used to transfer a pattern for delineating a circuit pattern of a semiconductor integrated circuit, includes preparing design data having a design pattern corresponding to the pattern to be transferred on a semiconductor substrate; generating resized data by enlarging the design data by a resizing quantity; generating first mask data by filling a space area having a space width of a space quantity or less of the resized data; and generating second mask data, to be aligned with the first mask data, having a window portion for selectively exposing an area determined by enlarging the space area by the resizing quantity.

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Notification of Reasons for Refusal mailed May 29, 2007, issued in copending Japanese Patent Application 2003-086563 by the Japanese Patent Office and English translation thereof.

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