Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-02
2008-03-25
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07350169
ABSTRACT:
A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more targets from the first target set and the structural product extraction is recursed for one or more next-state functions of a subset of the one or more registers. A sum-of-products form is recursed from the structural product extraction for one or more next-state functions of a subset of the one or more registers and a product-of-sums form of a result of the second recursing is decomposed to generate a decomposition of the product-of-sums form. The decomposition of the product-of-sums form is synthesized into a second target set and a subset of the second target set to recursively decompose is chosen. In response to the subset of the second target set being nonempty, the first target set is recursively decomposed and, in response to the second target set being empty, verification is applied to the second target set.
REFERENCES:
patent: 2006/0129959 (2006-06-01), Mang et al.
Bertacco et al., The Disjunctive Decomposition of Logic Functions, International Conference on Computer-Aided Design, 1997, pp. 78-82.
Sistla et al., Symmetry and Reduced Symmetry in Model Checking, International Conference on Computer Aided Verification, 2001, pp. 91-103.
Baumgartner Jason Raymond
Kanzelman Robert Lowell
Mony Hari
Paruthi Viresh
Dillon & Yudell LLP
Dinh Paul
International Business Machines - Corporation
Salys Casimer K.
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