Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-11
2008-09-09
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C365S201000
Reexamination Certificate
active
07424691
ABSTRACT:
A method for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
REFERENCES:
patent: 5392227 (1995-02-01), Hiserote
patent: 6185723 (2001-02-01), Burks et al.
patent: 6650592 (2003-11-01), Amatangelo et al.
patent: 6813201 (2004-11-01), Zarrineh et al.
patent: 2003/0037306 (2003-02-01), Gutwin, et al.
patent: 2003/0115035 (2003-06-01), Kulshreshtha et al.
patent: 2003/0163297 (2003-08-01), Khaira, et al.
patent: 2004/0162716 (2004-08-01), Dorfman et al.
patent: 2005/0273208 (2005-12-01), Yazawa et al.
patent: 2007/0044049 (2007-02-01), Adams et al.
U.S. Appl. No. 11/077,313, filed Mar. 10, 2005, Joshi et al.
U.S. Appl. No. 11/225,652, filed Sep. 13, 2005, Joshi et al.
U.S. Appl. No. 11/250,019, filed Oct. 13, 2005, Joshi et al.
U.S. Appl. No. 11/250,061, filed Oct. 13, 2005, Kuang et al.
U.S. Appl. No. 11/225,571, filed Sep. 13, 2005, Joshi et al.
Agarwal Vikas
Lee Michael Ju Hyeok
Shephard, III Philip G.
Garbowski Leigh Marie
Harris Andrew M.
Harris, Atty at Law, LLC Mitch
Salys Casimer K.
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