Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-02-19
2008-09-23
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07428714
ABSTRACT:
A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum line width, and associating a line width parameter with each line width marker, the line width parameter corresponding to a line width for the marked line. The line width parameters for each line width marker are compared to the actual layout line width.
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Ababei Adriana
Chevallier Christophe
Chiang Jack
Leffert Jay & Polglaze P.A.
Memula Suresh
Micro)n Technology, Inc.
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