Method of incorporating stress into a transistor channel by...

Details Method of incorporating stress into a transistor channel by... Method of incorporating stress into a transistor channel by...

2004-07-28

2008-07-22

Wilczewski, M. (Department: 2822)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S778000, C438S782000

Reexamination Certificate

active

07402535

ABSTRACT:
The present invention provides the method includes forming source/drain regions170in a semiconductor wafer substrate110adjacent a gate structure130located on a front side of the semiconductor wafer substrate110. The source/drain regions170have a channel region175located between them. A first stress-inducing layer190is placed on a backside of the semiconductor wafer substrate110and is subjected to a thermal anneal to cause a stress to form in the channel region175.

REFERENCES:
patent: 6306766 (2001-10-01), Sandhu et al.
patent: 6656853 (2003-12-01), Ito
patent: 6806178 (2004-10-01), Segawa
patent: 7009226 (2006-03-01), Sun
patent: 7053400 (2006-05-01), Sun et al.
patent: 7087474 (2006-08-01), Mitsuda et al.
patent: 7105394 (2006-09-01), Hachimine et al.
patent: 7115954 (2006-10-01), Shimizu et al.
patent: 7205615 (2007-04-01), Tsutsui et al.
patent: 2004/0018392 (2004-01-01), Yoder
patent: 408227834 (1996-09-01), None

Affiliated with

Also associated with

Rating

Method of incorporating stress into a transistor channel by... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of incorporating stress into a transistor channel by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of incorporating stress into a transistor channel by... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3973336