Method of manufacturing a semiconductor integrated circuit,...

Details Method of manufacturing a semiconductor integrated circuit,... Method of manufacturing a semiconductor integrated circuit,...

2006-02-16

2008-09-09

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07424695

ABSTRACT:
A method for manufacturing a semiconductor integrated circuit uses layout data designed by a sequence of processes. The sequence of processes includes disposing a lower-layer wiring pattern on an imaginary lower-layer wiring layer and an upper-layer wiring pattern perpendicular to the lower-layer wiring pattern on an imaginary upper-layer wiring layer implemented in the graphics image space, providing a detour pattern including a first detour pattern connected to the upper-layer wiring pattern, providing a plurality of via patterns connecting the lower-layer and upper-layer wiring patterns, and forming a via cell pattern.

REFERENCES:
patent: 6496968 (2002-12-01), Yamada et al.
patent: 6858928 (2005-02-01), Teig et al.
Gang Xu, et al., “Redundant-Via Enhanced Maze Routing for Yield Improvement”, Proc of ASPDAC, 2005, 4 Pages.

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