System and method for testing internal nodes of an integrated ci

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3241581, G01R 3128

Patent

active

057937770

ABSTRACT:
A system is provided with scanning capability that can capture data for each internal node at any predetermined machine cycle. The scanning mechanism scans a set of combinational logic and uses the system clock to gate the input to the scanning mechanism. A series of stages are provided in accordance with the number of internal nodes which are not externally connected, and provide input to an internal storage element. Each stage includes a scan latch for storing the data from the previous stages, as well as a latch to store data from the node associated with that particular stage. The cumulative data outputs from the previous stages are multiplexed with the data associated with the present stage and sequentially output, from a third latch, to subsequent stages. In this manner, the scan data is compiled for the internal nodes and output from the final stage in the sequential scanning system of the present invention. A test apparatus is connected to the scan inputs and outputs of the stages to record the scan data for subsequent analysis. The input latches in each stage are gated by the system clock and are capable of storing values for any given machine cycle.

REFERENCES:
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patent: 4742293 (1988-05-01), Koo et al.
patent: 4833676 (1989-05-01), Koo
patent: 4961013 (1990-10-01), Obermeyer, Jr. et al.
patent: 5453993 (1995-09-01), Kitaguchi et al.
patent: 5488613 (1996-01-01), Sridhar

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