Logic circuit combining exclusive OR gate and exclusive NOR...

Electronic digital logic circuitry – Exclusive function

Reexamination Certificate

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Details

C326S054000, C326S104000, C326S113000

Reexamination Certificate

active

07429872

ABSTRACT:
A logic circuit combining an exclusive OR gate and an exclusive NOR gate is provided. The logic circuit includes an NMOS transistor, a PMOS transistor, and first and second inverters. The NMOS transistor has a source connected to a first input signal, a drain connected to a first output signal, and a gate connected to a second input signal. The PMOS transistor has a source connected to the first input signal, a drain connected to a second output signal, and a gate connected to the second input signal. The first inverter receives the first output signal and outputs the second output signal. The second inverter receives the second output signal and outputs the first output signal.

REFERENCES:
patent: 4716312 (1987-12-01), Mead et al.
patent: 5633603 (1997-05-01), Lee
patent: 5818255 (1998-10-01), New et al.
patent: 06125267 (1994-05-01), None
patent: 08139591 (1996-05-01), None
patent: 09116252 (1996-05-01), None
patent: 11074781 (1999-03-01), None
patent: 1992 0022303 (1992-12-01), None
patent: 1998 0033074 (1998-09-01), None
English Abstract***.

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