Integrated circuit memory with back end mode disable

Details Integrated circuit memory with back end mode disable Integrated circuit memory with back end mode disable

1997-03-27

1998-08-11

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Having fuse element

365 96, 365195, 3652385, 36518901, G11C 700

Patent

active

057936927

ABSTRACT:
A memory circuit is described which can operate in one of a number of operating modes. The operating mode of the memory circuit can be changed in a non-volatile manner after the memory circuit is packaged to reduce production scrap or meet market demands. Disable circuitry is described which includes an anti-fuse that can be externally selectively blown to disable an operating mode. Control circuitry included in the memory circuit enables a new operating mode after the first operating mode is disable. A method of selectively disabling an operating mode is described. A hierarchical scheme is also described for enabling a new operating mode from a group of operating modes, for example page-mode, extended data output (EDO), or burst EDO.

REFERENCES:
patent: 4833650 (1989-05-01), Hirayama et al.
patent: 4876671 (1989-10-01), Norwood et al.
patent: 4891794 (1990-01-01), Hush et al.
patent: 4984216 (1991-01-01), Toda et al.
patent: 4990800 (1991-02-01), Lee
patent: 4996672 (1991-02-01), Kim
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5148391 (1992-09-01), Zagar
patent: 5159676 (1992-10-01), Wicklund et al.
patent: 5200652 (1993-04-01), Lee
patent: 5208177 (1993-05-01), Lee
patent: 5233206 (1993-08-01), Lee et al.
patent: 5241496 (1993-08-01), Lowrey et al.
patent: 5245577 (1993-09-01), Duesman et al.
patent: 5250459 (1993-10-01), Lee
patent: 5257222 (1993-10-01), Lee
patent: 5257225 (1993-10-01), Lee
patent: 5282158 (1994-01-01), Lee
patent: 5301159 (1994-04-01), Lee
patent: 5301164 (1994-04-01), Miyawaki
patent: 5315177 (1994-05-01), Zagar et al.
patent: 5324681 (1994-06-01), Lowrey et al.
patent: 5331196 (1994-07-01), Lowrey et al.
patent: 5331593 (1994-07-01), Merritt et al.
patent: 5335202 (1994-08-01), Manning et al.
patent: 5349566 (1994-09-01), Merritt et al.
patent: 5379250 (1995-01-01), Harshfield
patent: 5388248 (1995-02-01), Robinson et al.
patent: 5408435 (1995-04-01), McClure et al.
patent: 5410507 (1995-04-01), Tazunoki et al.
patent: 5583815 (1996-12-01), Enoi et al.
patent: 5657293 (1997-08-01), Merritt et al.
"EDO DRAM", 1995 Micron DRAM Data Book, Micron Technology Inc., Boise, Idaho, 1-1 to 1-46, (1995).
"Wide DRAM", 1993 Micron Specialty DRAM Data Book, Micron Technology Inc., Boise, Idaho, 1-1 to 1-16, (1993).

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