Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1988-07-21
1989-06-06
Beck, Shrive
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
427 96, 427 99, 427307, B05D 512
Patent
active
048370517
ABSTRACT:
A process is disclosed for filling contact or via openings in an integrated circuit with electrically conductive plugs. The process includes the steps of (a) forming one or more openings in an planarized oxide layer, where the one or more openings is disposed over and exposes semi-insulating or conductive regions, and (b) filling the one or more openings with conductive material to substantially the same level as the adjacent surfaces of the oxide layer to form respective planarized conductive plugs.
A further aspect of the invention is directed to a process which includes the steps of (a) forming first one or more openings of a first predetermined depth in a planarized oxide layer, the first one or more openings being disposed over the exposing respectively associated semi-insulating or conductive regions; (b) partially filling the first one or more openings with conductive material to a level corresponding to a second predetermined depth; (c) forming second one or more openings of the second predetermined depth in the planarized oxide layer, the second one or more openings being disposed over the exposing respectively associated semi-insulating or conductive regions; and (d) filling the first and second one or more openings to substantially the same level to form respective planarized plugs in the opeinings.
REFERENCES:
patent: 4332839 (1982-06-01), Levinstein
patent: 4378383 (1983-03-01), Moritz
patent: 4465716 (1984-08-01), Baber
patent: 4624864 (1986-11-01), Hartmann
IBM Technical Disclosure Bulletin, vol. 29, No. 1, Jun. 1986, "Variable Depth Contact Hole Preparation Utilizing A Nucleation Layer and Selective Chemical Vapor Deposition for Stud Formation", pp. 310-311.
IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, "Low Contact Resistance, Self-Aligned Metal Stud Process", p. 1401.
S. M. SZE: "VLSI Technology", 1985, McGraw-Hill, p. 369.
Chin Maw R.
Farb Joseph E.
Beck Shrive
Dang Vi Duong
Float Kenneth W.
Gudmestad Terje
Hughes Aircraft Company
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