Data processing system with bus access retraction

Details Data processing system with bus access retraction Data processing system with bus access retraction

2004-09-30

2008-03-04

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S040000, C710S041000, C710S042000, C710S043000, C710S107000, C710S125000, C710S305000

Reexamination Certificate

active

07340542

ABSTRACT:
A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst
on-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

REFERENCES:
patent: 4620278 (1986-10-01), Ellsworth et al.
patent: 4987529 (1991-01-01), Craft et al.
patent: 2002/0144054 (2002-10-01), Fanning et al.
M-CORE M210 Specification, Version 1.5; Feb. 17, 1999; 2pp (Cover & Preface); pp. iii-xiv (Table of Contents), pp. 159-210; Motorola Inc., USA.
AMBA™ Specification (Rev 2.0); May 13, 1999; pp. i-xii; pp. 1-1 to 1-14; pp. 2-1 to 2-8, pp. 3-1 to 3-58; ARM.

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