Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2002-05-29
2008-03-04
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S167000
Reexamination Certificate
active
07340577
ABSTRACT:
A method and system for efficiently executing reads after writes in a memory. The system includes a memory controller and a memory core interfacing with the memory controller. The memory operates with a read data latency and a similar write data latency, and the memory immediately processes a read in a read-after-write situation. The system further includes a control circuit for controlling the memory and detecting an address collision between the read and a previously issued write and, in response thereto, stalling the memory by delaying issuance of the read to the memory until after the previously issued write completes.
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Montrym John S.
Van Dyke James M.
Diller Jesse
NVIDIA Corporation
Sparks Donald
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