Software accessible fast VA to PA translation

Details Software accessible fast VA to PA translation Software accessible fast VA to PA translation

Filed on

2005-01-11

Date issued

2008-03-25

Examiner

Peugh, Brian R. (Department: 2187)

Patent Class

Electrical computers and digital processing systems: memory

SubClass

Address formation

SubSubClass

Address mapping

Other Related Categories

C711S205000, C711S208000, C711S221000

Type

Reexamination Certificate

Status

active

Patent number

07350053

Description

ABSTRACT:
A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address translated by the TLB into a register within a processor and transmitting the data from the physical address to a destination computing device.

REFERENCES:
patent: 5873123 (1999-02-01), Patel et al.
patent: 6456891 (2002-09-01), Kranich et al.
patent: 6681311 (2004-01-01), Gaskins et al.
patent: 2004/0139295 (2004-07-01), Arimilli et al.
Saulsbury, Ashley. “Recency-Based TLB Preloading”. 2000. ACM.

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