Semiconductor dual guardring arrangement

Details Semiconductor dual guardring arrangement Semiconductor dual guardring arrangement

2008-03-25

2008-03-25

Menz, Douglas M. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S362000

Reexamination Certificate

active

11447359

ABSTRACT:
A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions. In particular, an inner guard that is located closer to an active area provides desirable performance during normal operating conditions, while an outer guardring located further from the active area provides desirable performance during an ESD event.

REFERENCES:
patent: 5045913 (1991-09-01), Masleid et al.
patent: 6900969 (2005-05-01), Salling et al.
patent: 6940131 (2005-09-01), Baldwin et al.
patent: 2005/0007216 (2005-01-01), Baldwin et al.

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