Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-04-15

2008-04-15

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230010, C365S230030, C365S230060

Reexamination Certificate

active

11500262

ABSTRACT:
A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting operation and generating a redundant enable signal when the defective addresses are applied during an operation. The redundant decoder including decoders selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, a corresponding block address, and a lower and upper block address, wherein each of the of decoders is electrically connected to one of the lower and upper blocks.

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patent: 10003798 (1998-01-01), None
patent: 2002025288 (2002-01-01), None
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patent: 20030002802 (2003-09-01), None
English Abstract for Publication No. 1995-0020754.
English Abstract for Publication No. 10-003798.
English Abstract for Publication No. 2002-025288.
English Abstract for Publication No.: 1020030002802.

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