Optimization of NMOS drivers using self-ballasting ESD...

Details Optimization of NMOS drivers using self-ballasting ESD... Optimization of NMOS drivers using self-ballasting ESD...

2008-01-08

2008-01-08

Tran, Thien F (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S361000

Reexamination Certificate

active

11055145

ABSTRACT:
Design and optimization of NMOS drivers using a self-ballasting ESD protection technique in a fully silicided CMOS process. Silicided NMOS fingers which include segmented drain diffusion. Specifically, the segmented drain diffusion provides self-ballasting resistors which improves the ESD performance. Preferably, the width of the each diffusion resistor is relatively small, as this can improve a non-uniform silicidation process. The resistance of the segmented diffusion resistors is determined by their width and length, and effectively increases the ballasting effect of parasitic n-p-n bipolar transistors.

REFERENCES:
patent: 5742083 (1998-04-01), Lin
patent: 6864536 (2005-03-01), Lin et al.
patent: 2004/0164356 (2004-08-01), Mergens et al.
Keppens, Bart et al., “Active-Area-Segmentation (AAS) Technique for Compact, ESD Robust, Fully Silicided NMOS Design”, EOS/ESD Symposium, 2003.
Verhaege, Koen G. et al., “Novel Design of Driver and ESD Transistors with Significantly Reduced Silicon Area”, Sarnoff and Sarnoff Europe, 2001.

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