Semiconductor memory device with channel regions along...

Details Semiconductor memory device with channel regions along... Semiconductor memory device with channel regions along...

2008-07-01

2008-07-01

Lee, Eugene (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S239000, C257S278000, C257SE21014, C257S288000, C257SE29309

Reexamination Certificate

active

11304062

ABSTRACT:
A semiconductor memory (26) having a plurality of memory cells (25), the semiconductor memory (26) having a substrate (1), at least one wordline (2) and first (3) and second lines (4). Each memory cell (25) of the plurality of memory cells (25) includes a fin (15) of semiconductor material, the fin (15) having a top surface (5), first (6) and second (7) opposing sidewalls and first (8) and second (9) opposing ends. The fin (15) extends along a first direction (X). Each memory cell (25) also includes a charge-trapping layer (11) disposed on the first (6) and second (7) sidewalls of said fin (15), a patterned first insulating layer (10) disposed on the top surface (5) of the fin (15), wherein the first insulating layer (10) abuts the top surface (5) of the fin (15) and the charge-trapping layer (11). Each memory cell (25) also includes a first doping region (12) coupled to the first end (8) of said fin (15) and a second doping region (13) coupled to the second end (9) of the fin (15).

REFERENCES:
patent: 6657252 (2003-12-01), Fried et al.
patent: 6861685 (2005-03-01), Choi
patent: 7227234 (2007-06-01), Roizin et al.
patent: 2004/0207001 (2004-10-01), Kouznetsov et al.
patent: 2005/0260814 (2005-11-01), Cho et al.
patent: 2006/0071259 (2006-04-01), Verhoeven

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