Priority registers for biasing access to shared resources

Details Priority registers for biasing access to shared resources Priority registers for biasing access to shared resources

2008-05-27

2008-05-27

Myers, Paul R. (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

Hierarchical or multilevel arbitrating

C710S116000, C710S240000, C718S103000

Reexamination Certificate

active

11051148

ABSTRACT:
A priority register is provided for each of a multiple processor cores of a chip multiprocessor, where the priority register stores values that are used to bias resources available to the multiple processor cores. Even though such multiple processor cores have their own local resources, they must compete for shared resources. These shared resources may be stored on the chip or off the chip. The priority register biases the arbitration process that arbitrates access to or ongoing use of the shared resources based on the values stored in the priority registers. The way it accomplishes such biasing is by tagging operations issued from the multiple processor cores with the priority values, and then comparing the values within each arbiter of the shared resources.

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