Use of models in integrated circuit fabrication

Details Use of models in integrated circuit fabrication Use of models in integrated circuit fabrication

2008-04-15

2008-04-15

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C700S121000

Reexamination Certificate

active

11142606

ABSTRACT:
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

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