System and method for designing a delayer emulation model

Details System and method for designing a delayer emulation model System and method for designing a delayer emulation model

2008-04-08

2008-04-08

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11285661

ABSTRACT:
A system for designing a delayer emulation model (1) includes a delayer emulation model generating apparatus (2). The delay emulation model generating apparatus includes: a delay circuit defining module (20) for defining delay parameters of a delay circuit, and generating the delay circuit; a delay signal setting module (21) for setting a delay interval for the transition from a high voltage to a low voltage and a delay interval for the transition from a low voltage to a high voltage of an input delay signal; a voltage regulation circuit defining module (22) for defining voltage parameters of a voltage regulation circuit, and generating the voltage regulation circuit; a voltage regulating module (23) for regulating a voltage of the input delay signal from the delay circuit according to requirements of an output delay signal; and a model calling module (24) for generating the delayer emulation model by means of calling the delay circuit and the voltage regulation circuit.

REFERENCES:
patent: 5268894 (1993-12-01), Ogawa et al.
patent: 2002/0147605 (2002-10-01), Southworth et al.

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