Semiconductor memory and semiconductor device having SOI structu

Details Semiconductor memory and semiconductor device having SOI structu Semiconductor memory and semiconductor device having SOI structu

1995-06-05

1997-06-03

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257206, 257297, 257350, 257351, 257394, 257400, 257409, 438154, H01L 2712

Patent

active

056357443

ABSTRACT:
A semiconductor memory and device comprising a plurality of N-channel and P-channel transistor regions, a first and a second field shield region, and an oxide isolation region. The first field shield region is disposed so as to isolate the N-channel transistor regions from one another, and the second field shield region is provided to isolate the P-channel transistor regions from one another. The oxide isolation region is furnished to isolate the N-channel transistor regions from the P-channel transistor regions. The isolation effected by the field shield regions and the isolation provided by the oxide isolation region combine to suppress latch-up, fix the potential in the body regions of the MOS transistors making up the memory or device, and minimize the layout area of the memory or device.

REFERENCES:
patent: 4946799 (1990-08-01), Blake et al.
patent: 4965213 (1990-10-01), Blake
patent: 5001528 (1991-03-01), Bahraman
patent: 5079860 (1992-01-01), Blake
patent: 5125007 (1992-06-01), Yamaguchi et al.
patent: 5440161 (1995-08-01), Iwamatsu et al.
patent: 5463238 (1995-10-01), Takahashi et al.

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