Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-01-29
2008-01-29
Parker, Kenneth (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S393000, C257SE27098, C257SE27099
Reexamination Certificate
active
11172931
ABSTRACT:
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
REFERENCES:
patent: 4984200 (1991-01-01), Saitoo et al.
patent: 5072286 (1991-12-01), Minami et al.
patent: 5126285 (1992-06-01), Kosa et al.
patent: 5162259 (1992-11-01), Kolar et al.
patent: 5194749 (1993-03-01), Meguro et al.
patent: 5237187 (1993-08-01), Suwanai et al.
patent: 5239196 (1993-08-01), Ikeda et al.
patent: 5324961 (1994-06-01), Rodder
patent: 5388067 (1995-02-01), Sato et al.
patent: 5426324 (1995-06-01), Raieevakumar
patent: 5483083 (1996-01-01), Meguro et al.
patent: 5523966 (1996-06-01), Idei et al.
patent: 5530807 (1996-06-01), Baker et al.
patent: 5631863 (1997-05-01), Fechner et al.
patent: 5635731 (1997-06-01), Ashida
patent: 5652457 (1997-07-01), Ikeda et al.
patent: 5684315 (1997-11-01), Uchiyama et al.
patent: 5780910 (1998-07-01), Hashimoto et al.
patent: 5834851 (1998-11-01), Ikeda et al.
patent: 5858845 (1999-01-01), Cheffings
patent: 2001/0023965 (2001-09-01), Ikeda et al.
patent: 0342466 (1989-11-01), None
patent: 62-154296 (1987-07-01), None
patent: 02-087392 (1990-03-01), None
patent: 2-103795 (1990-04-01), None
patent: 3-114256 (1991-05-01), None
patent: 3-183162 (1991-08-01), None
patent: 3-234058 (1991-10-01), None
patent: 4-180262 (1992-06-01), None
patent: 05-275645 (1993-10-01), None
patent: 6-151771 (1994-05-01), None
patent: 7-161844 (1995-06-01), None
patent: 1993-0005215 (1993-03-01), None
patent: 1994-0016879 (1994-07-01), None
patent: WO 02/061840 (2002-08-01), None
Verhaar, et al., “A 25 μm2bulk Full CMOS SRAM Cell Technology with Fully Overlapping contacts”, Philips Research Laboratories, 1990 IEEE, 18.2.1-18.2.4.
Office Action dated Jun. 25, 2002, in corresponding Japanese Patent Application.
Korean Office Action, dated Apr. 27, 2005 for Application No. 10-2004-0048902.
Hashimoto Naotaka
Hoshino Yutaka
Ikeda Shuji
Antonelli, Terry Stout & Kraus, LLP.
Parker Kenneth
Renesas Technology Corp.
Warren Matthew E.
LandOfFree
Method of manufacturing semiconductor integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor integrated circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3932681