Semiconductor memory device and method for biasing dummy...

Details Semiconductor memory device and method for biasing dummy... Semiconductor memory device and method for biasing dummy...

2008-07-29

2008-07-29

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S175000, C365S210100

Reexamination Certificate

active

11695232

ABSTRACT:
A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

REFERENCES:
patent: 6504752 (2003-01-01), Ito
patent: 7215587 (2007-05-01), Lee et al.
patent: 2008/0002457 (2008-01-01), Toda et al.

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