System for determining status of multiple interlocking FIFO...

Details System for determining status of multiple interlocking FIFO... System for determining status of multiple interlocking FIFO...

2008-09-09

2008-09-09

Hafiz, Tariq (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

Reexamination Certificate

active

10869701

ABSTRACT:
One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

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