Input buffer with optimal biasing and method thereof

Details Input buffer with optimal biasing and method thereof Input buffer with optimal biasing and method thereof

2008-09-16

2008-09-16

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S090000, C326S115000, C326S127000

Reexamination Certificate

active

11347477

ABSTRACT:
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.

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