Inverting dynamic register with data-dependent hold time...

Details Inverting dynamic register with data-dependent hold time... Inverting dynamic register with data-dependent hold time...

2008-04-15

2008-04-15

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000

Reexamination Certificate

active

11332496

ABSTRACT:
Dynamic logic register including evaluation logic, delay logic, latching logic, and a keeper circuit. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generates a kill signal, where the kill signal is a delayed version of a clock signal, and where the delay between the clock and kill signals comprises a hold time, and where the hold time is shortened when the logic function evaluates to the first state. The latching logic is responsive to the clock and kill signals and the state of pre-charged node, and controls the state of an output node based on the state of a pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of the kill signal, and otherwise presents a tri-state condition to said output node.

REFERENCES:
patent: 5075386 (1991-12-01), Vanderbilt
patent: 5889979 (1999-03-01), Miller, Jr. et al.
patent: 6191618 (2001-02-01), Gayles et al.
patent: 6496038 (2002-12-01), Sprague et al.
patent: 6628143 (2003-09-01), Hsu et al.
patent: 6650145 (2003-11-01), Ngo et al.
patent: 6965254 (2005-11-01), Lundberg
patent: 7212039 (2007-05-01), Qureshi et al.
patent: 2002/0158670 (2002-10-01), Alvandpour
patent: 2003/0042932 (2003-03-01), Bales
patent: 2003/0052714 (2003-03-01), Alvandpour
patent: 2003/0110404 (2003-06-01), Seningen et al.
patent: 2004/0034681 (2004-02-01), Bertram
patent: 2004/0113658 (2004-06-01), Lundberg
patent: 2005/0046446 (2005-03-01), Qureshi et al.
patent: 2005/0127952 (2005-06-01), Bertram
patent: 2006/0033534 (2006-02-01), Lundberg et al.

Affiliated with

Also associated with

Rating

Inverting dynamic register with data-dependent hold time... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Inverting dynamic register with data-dependent hold time..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Inverting dynamic register with data-dependent hold time... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3919735