Semiconductor integrated circuit with full-speed data...

Details Semiconductor integrated circuit with full-speed data... Semiconductor integrated circuit with full-speed data...

2008-07-22

2008-07-22

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

10293576

ABSTRACT:
The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem.

REFERENCES:
patent: 6043694 (2000-03-01), Dortu
patent: 6154419 (2000-11-01), Shakkarwar
patent: 6337830 (2002-01-01), Faue
patent: 6574163 (2003-06-01), Maeda
patent: 6597628 (2003-07-01), Kerl
patent: 2003/0031082 (2003-02-01), Sawada
patent: 2003/0120989 (2003-06-01), Zumkehr

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