Integrated circuit having multiple LDD and/or source/drain impla

Details Integrated circuit having multiple LDD and/or source/drain impla Integrated circuit having multiple LDD and/or source/drain impla

1997-01-10

1998-08-11

Wallace, Valencia Martin

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257346, 257347, 438302, 438305, H01L 2976, H01L 2994

Patent

active

057930902

ABSTRACT:
An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.

REFERENCES:
patent: 5308780 (1994-05-01), Chou et al.
patent: 5440165 (1995-08-01), Mitsunaga et al.
patent: 5516711 (1996-05-01), Wang
patent: 5567965 (1996-10-01), Kim
patent: 5591650 (1997-01-01), Hsu et al.

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